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pfs7323-7329 hiperpfs-2 family www.powerint.com june 2013 high power pfc controller with integrated high-voltage mosfet and qspeed ? diode ? key benefts ? highly integrated for smallest boost pfc form factor ? integrated controller and mosfet in all package options ? ultra-low reverse recovery loss diode (qspeed) included in extended esip? package option ? lossless internal current sense reduces component count and system losses ? en61000-3-2 class c and d compliant ? packaging optimized for high volume production ? exposed pad connected to ground pin (coolpad) ? eliminates insulating pad/heat-spreader ? enhanced features ? programmable power good (pg) signal ? user selectable power limit: enables device swapping in a given design to optimize effciency/cost ? integrated non-linear amplifer for fast output ov and uv protection ? high effciency and power factor across load range ? >95% effciency from 10% load to full load ? <200 mw no-load consumption at 230 vac in remote off-state ? light load pf >0.9 at 20% load on optimized designs >200 w ? pf >0.95 at 50% load ? enables 80+ platinum designs ? frequency adjusted over line voltage and each line cycle ? spread-spectrum across >60 khz window simplifes emi fltering requirements ? lower boost inductance ? provides up to 425 w peak output power ? >425 w peak power in power limit voltage regulation mode figure 1. typical application schematic. output power table esip-16 package product maximum continuous output power rating at 90 vac (in full mode) peak output power rating full mode (r = 24.9 k w ) pfs7323l 110 w 120 w PFS7324L 130 w 150 w pfs7325l 185 w 205 w pfs7326h 230 w 260 w pfs7327h 290 w 320 w pfs7328h 350 w 385 w pfs7329h 380 w 425 w table 1. output power table (see table 2 on page 11 for maximum continuous output power ratings.) pi-6691-050313 ac in dc out + s c pgt fb vcc pg k d r g v control hiperpfs-2 vcc ? protection features include: uv, ov, otp, brown-in/out, cycle-by-cycle current limit and power limiting for overload protection ? halogen free and rohs compliant applications ? pc ? high-power adaptors ? printer ? high-power led lighting ? lcd tv ? industrial and appliance ? video game consoles ? generic pfc converters
rev. b 06/13 2 pfs7323-7329 www.powerint.com description the hiperpfs-2 device family members reach a very high level of integration including a continuous conduction mode (ccm) boost pfc controller, gate driver, ultra-low reverse recovery (qspeed) diode (eesip? package options) and high-voltage power mosfet in a single, low-profle coolpad (ground pin connected) power package that is able to provide near unity input power factor. the hiperpfs-2 devices eliminate the pfc converters need for external current sense resistors, the power loss associated with those components, and leverages an innovative control technique that adjusts the switching frequency over output load, input line voltage, and even input line cycle. this control technique is designed to maximize effciency over the entire load range of the converter, particularly at light loads. additionally, this control technique signifcantly minimizes the emi fltering requirements due to its wide bandwidth spread spectrum effect. the hiperpfs-2 also features an integrated non-linear amplifer for enhanced load transient response, a user programmable power good (pg) signal as well as user selectable power limit functionality. hiperpfs-2 includes power integrations standard set of comprehensive protection features, such as integrated soft-start, uv, ov, brown-in/out, and hysteretic thermal shutdown. hiperpfs-2 also provides cycle-by-cycle current limit for the power mosfet, power limiting of the output for overload protection, and pin-to-pin short-circuit protection. hiperpfs-2s innovative variable frequency continuous conduction mode of operation (vf-ccm) minimizes switching losses by maintaining a low average switching frequency, while also varying the switching frequency in order to suppress emi, the traditional challenge with continuous conduction mode solutions. systems using hiperpfs-2 typically reduce the total x and y capacitance requirements of the converter, the inductance of both the boost choke and emi noise suppression chokes, reducing overall system size and cost. additionally, compared with designs that use discrete mosfets and controllers, hiperpfs-2 devices dramatically reduce component count and board footprint while simplifying system design and enhancing reliability. the innovative variable frequency, continuous conduction mode controller enables the hiperpfs-2 to realize all of the benefts of continuous conduction mode operation while leveraging low-cost, small, simple emi flters. many regions mandate high power factor for many electronic products with high power requirements. these rules are combined with numerous application-specifc standards that require high power supply effciency across the entire load range, from full load to as low as 10% load. high effciency at light load is a challenge for traditional pfc approaches in which fxed mosfet switching frequencies cause fxed switching losses on each cycle, even at light loads. besides featuring relatively fat effciency across the load range, hiperpfs-2 also enables higher power factor at light loads. hiperpfs-2 simplifes compliance with new and emerging energy-effciency standards over a broad market space in applications such as pcs, lcd tvs, notebooks, appliances, pumps, motors, fans, printers, and led lighting. hiperpfs-2 advanced power packaging technology and high effciency simplifes the complexity of mounting the package and thermal management, while providing very high power capabilities in a single compact package; these devices are suitable for pfc applications from 75 w to 425 w. product highlights protected power factor correction solution ? incorporates high-voltage power mosfet, ultra-low reverse recovery loss qspeed diode, controller, and gate driver ? en61000-3-2 class d and class c compliance ? integrated protection features reduce external component count ? accurate built-in brown-in/out protection ? accurate built-in undervoltage (uv) protection ? accurate built-in overvoltage (ov) protection ? hysteretic thermal shutdown (otp) ? internal power limiting function for overload protection ? cycle-by-cycle power switch current limit ? internal non-linear amplifer for enhanced load transient response ? no external current sense required ? provides lossless internal sensing via sense-fet ? reduces component count and system losses ? minimizes high current gate drive loop area ? minimizes output overshoot and stresses during start-up ? integrated power limit and frequency soft-start ? improved dynamic response ? input line feed-forward gain adjustment for constant loop gain across entire input voltage range ? eliminates up to 40 discrete components for higher reliability and lower cost intelligent solution for high effciency and low emi ? continuous conduction mode pfc uses novel constant volt/ amp-second control engine ? high effciency across load ? high power factor across load ? low cost emi flter ? frequency sliding technique for light load effciency improvements ? >95% effciency from 10% load to full load at nominal input voltages ? variable switching frequency to simplify emi flter design ? varies over line input voltage to maximize effciency and minimize emi flter requirements ? varies with input line cycle voltage by >60 khz to maximize spread spectrum effect advanced package for high power applications ? up to 425 w peak output power capability in a highly compact package ? simple adhesive or clip mounting to heat sink ? no insulation pad required and can be directly connected to heat sink ? staggered pin arrangement for simple routing of board traces and high-voltage creepage requirements ? single package solution for pfc converter reduces assembly costs and layout size
rev. b 06/13 3 pfs7323-7329 www.powerint.com pin functional description voltage monitor (v) pin: the voltage monitor pin is tied to the rectifed high-voltage dc rail through a large resistor (4 m w 1%) to minimize power dissipation and standby power consumption. modifying this resistor value affects peak power limit, brown-in/out thresholds and will degrade input current quality (reduce power factor and increase thd). a small ceramic capacitor (22 nf) is required from the voltage monitor pin to signal ground pin to bypass any switching noise present on the rectifed dc bus. this pin also features brown-in/out detection thresholds. reference (r) pin: this pin is connected to an external precision resistor and is used for an internal current reference source in the controller. the external resistor is tied between the reference and signal ground pins. the reference pin only has two valid resistor values to select full (24.9 k w 1%) and effciency (49.9 k w 1%) power modes. a precision resistor with the values specifed above must be selected since this sets the internal current reference for the controller. other values beyond what is specifed may adversely effect the operation of the device. a bypass capacitor is also recommended across the reference pin resistor to the signal ground pin. for full power mode (24.9 k w ) a capacitor value of 470 pf and 1 nf for the effciency mode with 49.9 k w . signal ground (g) pin: discrete components used in the feedback circuit, including loop compensation, decoupling capacitors for the supply (vcc) and line-sense (v) must be referenced to the signal ground pin. the signal ground pin is also connected to the tab of the device. the signal ground pin must not be tied to the source pin . compensation (c) pin: this pin is used for loop compensation and voltage feedback. the compensation pin is a high input-impedance reference terminal that connects to the main voltage regulation feedback resistor divider network. this pin also connects to the loop compensation components comprising of a series rc network. a 22 nf capacitor is also required between the compensation and signal ground pins; this capacitor must be placed very close to the device on the pcb to bypass any switching noise. feedback (fb) pin: this pin is connected to the main voltage regulation feedback resistor divider network and is used for fast over and under- voltage protection. this pin also detects the presence of the main voltage divider network at start-up. power good threshold (pgt) pin: this pin is used to program the output voltage threshold where the pg signal becomes high-impedance representing the pfc stage falling out of regulation. the low threshold for the pg signal is programmed with a resistor between the power good threshold and signal ground pins. power good (pg) pin: this pin is an open-drain connection that indicates that the output voltage is in regulation. at start-up, once the feedback pin voltage has risen to ~95% of the set output voltage, the power good pin is pulled low. after start-up the output voltage threshold at which the pg signal becomes high- impedance depends on the threshold programmed by the power good threshold pin resistor. bias power (vcc) pin: this is a 10.2-13 vdc bias supply used to power the ic. the bias voltage must be externally clamped to prevent the bias power pin from exceeding 15 vdc. source (s) pin: this pin is the source connection of the power switch. drain (d) pin: this is the drain connection of the internal power switch. boost diode cathode (k) pin: (esip-16 package only) this is the cathode connection of the internal qspeed diode. pi-6789-022213 h package (esip-16d) ( front view) h package (esip-16d) (back view) l package (esip-16g) ( front view) 16 v r g c fb pg pgt vcc d k 16 k s s 13 d 13 nc 14 nc 14 11 s 11 9 vcc 9 10 s 10 8 pgt 8 1 v 1 3 r 3 4 g 4 5 c 5 6 fb 6 7 pg 7 exposed pad (backside) internally connected to ground (g) pin exposed metal (both h and l packages) (on package edge) internally connected to g pin 1 3 4 5 6 7 8 9 10 11 13 14 16 pin 1 i.d. pin 1 i.d. g g v r g c fb pg pgt vcc d k s s nc exposed pad (backside) not shown figure 2. pin confguration.
rev. b 06/13 4 pfs7323-7329 www.powerint.com figure 3. functional block diagram. functional description the hiperpfs-2 is a variable switching frequency boost pfc solution. more specifcally, it employs a constant amp-second on-time and constant volt-second off-time control algorithm. this algorithm is used to regulate the output voltage and shape the input current to comply with regulatory harmonic current limits (high power factor). integrating the switch current and controlling it to have a constant amp-sec product over the on-time of the switch allows the average input current to follow the input voltage. integrating the difference between the output and input voltage maintains a constant volt-second balance dictated by the electro-magnetic properties of the boost inductor and thus regulates the output voltage and power. more specifcally, the control technique sets constant volt- seconds for the off-time (t off ). the off-time is controlled such that: # vv tk oi no ff 1 -= ^h (1) since the volt-seconds during the on-time must equal the volt-seconds during the off-time, to maintain fux equilibrium in the pfc choke, the on-time (t on ) is controlled such that: # vt k in on 1 = (2) the controller also sets a constant value of charge during each on-cycle of the power mosfet. the charge per cycle is varied gradually over many switching cycles in response to load changes so it can be regarded as substantially constant for a half line cycle. with this constant charge (or amp-second) control, the following relationship is therefore also true: # it k in on 2 = (3) substituting t on from (2) into (3) gives: iv k k in in 1 2 # = (4) pi-6697-050312 + - bias power (vcc) boost diode cathode (k) drain (d) source (s) ground (g) power good (pg) power good threshold (pgt) feedback (fb) compensation (c) reference (r) v cc+ internal supply reference and band gap soft- start voltage monitor (v) m on input line interface peak detector i vpk i v input uv (i uv+ /i uv- ) + - + - + - + - fb ov ~(v o- v in ) internal reference v ref transconductance error-amplier feedback/ compensation pin ov/uv sensefet power mosfet c-uv/off comparator i ref i v m off (i ref - i v ) c int c uv / fb off / c off i ocp vref v pg(h) i pgt fbc ov fbc uv + + + - + - + - + - + - fbc uv fbc ov fb on / fb off v fb v cc buffer and de-glitch filter c uv /c off v fb v pg(h) v cc i pgt i ocp i s v off v e c int i vpk v off v e p on m on i s vcc latch comparator input uv otp soa timer supervisor comparator 1 khz filter frequency slide m on is the switch current sense scale factor which is a function of the peak input voltage ocp leb feedback-ovp/off comparator v off is a function of the error-voltage (v e ) and is used to reduce the average operating frequency as a function of output power fb gm fb gm
rev. b 06/13 5 pfs7323-7329 www.powerint.com pi-5335-111610 i s dt v e v off (v out -v in )dt latch reset latch set gate drive (q) maximum on-time minimum off-time timing supervisor figure 4. idealized converter waveforms. figure 5. typical normalized output voltage characteristics as function of normalized peak load rating figure 6. normalized minimum power limit as function of input voltage. 0 0.2 0.4 0.6 1 1.2 1.4 0.8 normalized to peak power rating normalized to set output voltage regulation threshold 1.2 1 0.8 0.6 0.4 0.2 0 pi-6216-113010 the relationship of (4) demonstrates that by controlling a constant amp-second on-time and constant volt-second off-time, the input current i in is proportional to the input voltage v in , therefore providing the fundamental requirement of power factor correction. this control produces a continuous mode power switch current waveform that varies both in frequency and peak current value across a line half-cycle to produce an input current proportional to the input voltage. control engine the controller features a low bandwidth error-amplifer which connects its non-inverting terminal to an internal voltage reference of 6 v. the inverting terminal of the error-amplifer is available on the external control pin which connects to the loop compensation and voltage divider network to regulate the output voltage. the feedback pin connects directly to the divider network for fast transient load response. the internal sense-fet switch current is integrated and scaled by the input voltage peak detector current sense gain (m on ) and compared with the error-amplifer signal (v e ) to determine the cycle on-time. internally the difference between the input and output voltage is derived and the resultant is scaled, integrated, and compared to a voltage reference (v off ) to determine the cycle off-time. careful selection of the internal scaling factors produce input current waveforms with very low distortion and high power factor. line feed-forward scaling factor (m on ) the voltage monitor (v) pin current is used internally to derive the peak of the input line voltage which is used to scale the gain of the current sense signal through the m on variable. this contribution is required to reduce the dynamic range of the control feedback signal as well as maintain a constant loop gain over the operating input line range. this line-sense feed- forward gain adjustment is proportional to the square of the peak rectifed ac line voltage and is adjusted as a function of voltage monitor pin current. the line-sense feed-forward gain is also important in providing a switch power limit over the input line range. besides modifying brown- in/out thresholds, the voltage monitor pin resistor also affects power limit of the device. this characteristic is optimized to maintain a relatively constant internal error-voltage level at full load from an input line of 100 to 230 vac input. beyond the specifed peak power rating of the device, the internal power limit feature will regulate the output voltage below the set regulation threshold as a function of output overload beyond the peak power rating. figure 5 illustrates the typical regulation characteristic as function of load. below the brown-in threshold (i uv+ ) the power limit is reduced when the device is operated in the full power mode as shown in the fgure below. as the input line voltage is reduced toward the brown-out threshold (i uv- ) and if the load exceeds the power limit derating the boost output voltage will drop out of regulation in accordance to figure 6. 70 75 80 85 95 100 90 input voltage (vac) normalized minimum power limit 1.2 1 0.8 0.6 0.4 0.2 0 pi-6940-013013
rev. b 06/13 6 pfs7323-7329 www.powerint.com figure 8. start-up sequence. the minimum rated peak power shown in table 1 is not derated below the brown-in threshold when the device is operated in the effciency mode. soft-start with pin-to-pin short-circuit protection the feedback pin which is connected to a resistor voltage divider provides a means to overcome the inherently slow feedback loop response. the controller has an integrated non-linear amplifer function to limit the maximum overshoot and undershoot during load transient events. to reduce switch and output diode current stress at start-up, the hiperpfs slews the internal error-voltage from zero to its steady-state value at start-up. figure 7 illustrates the relative relationship between the application of v cc and power limit soft-start function through the internal error-voltage. the error-voltage has a controlled slew rate of 0.25 v/ms at start-up, corresponding to the t soft time duration for a full scale error voltage of 5 v. the beginning of soft-start is gated by the v cc+ , reference, control and feedback pin voltage thresholds in the sequence described below. once the applied vcc is above the vcc+ threshold, conditions for reference, compensation soft-start check sequence is v cc > v cc+ ? apply 0.5 a on on fb pin to check open fb pin no yes apply pgt current source yes yes no yes is pg ?off? (pg high impedance)? feedback short to c pin start converter increase fb pin current to 20 a is the nla charging or discharging? is i r within bounds for ef?ciency or full mode? yes yes no no pi-6698-013013 yes no no no no source ~3 ma to c pin is v c > 3 v? no is otp ok? yes yes yes no is v fb > fb off v fb < fb ov ? yes no is v c > c off ? yes no is the nla charging or discharging? is iv > i uv+ ? yes yes yes is v v < 1 v? yes is v fb > fb off v fb < fb on v c > c off otp ok? yes no is i r within bounds for ef?ciency or full mode? yes decrease fb pin current to 0.5 a apply 6 ma v pin current sink yes set internal power limit remove 6 ma v pin current sink slow power limit over soft-start duration no is iv > i uv+ yes yes yes detect input voltage peak pi-5336-110810 internal error-voltage (v e ) v cc voltage t start-delay t soft v cc+ t ~5 v figure 7. power limit soft-start function.
rev. b 06/13 7 pfs7323-7329 www.powerint.com figure 9. (a) frequency variation over line half-cycle as a function of input voltage (b) frequency variation over line half-cycle as a function of load. 0 45 90 135 180 pi-6694-013013 120 230 va c 180 va c 135 va c 115 va c peak load 90 va c 110 100 90 80 70 60 50 40 30 20 10 fr equency (khz) line conduction angle () 0 45 90 135 180 pi-6695-013013 120 110 100 90 80 70 60 50 40 30 20 10 fr equency (khz) line conduction angle () 100% peak load 75% peak load v in = 115 va c 25% peak load 50% peak load expected fr equency range at peak rated load figure 10. v off vs. v e and v off vs. input voltage. and feedback pins are satisfed and the sensed voltage monitor pin current is above i uv+ ,the ic applies a ~6 ma current sink through the voltage monitor pin and checks that the status of the reference pin voltage is still in a valid range. this checks to ensure that the feedback and reference pins are not shorted together. in the event that these pin voltage are shorted or the reference pin current is no longer in the valid range, voltage monitor pin holds the 6 ma current sink indefnitely until the reference pin is in the valid range. figure 8 illustrates this sequence. timing supervisor and operating frequency range since the controller is expected to operate with a variable switching frequency over the line frequency half-cycle, typically spanning a range of 24 C 110 khz, the controller also features a timing supervisor function which monitors and limits the maximum switch on-time and off-time as well as ensures a minimum cycle off-time. ~5 v v in < ~ 140 vac v in > ~ 170 vac ~5 v (full power) ~140 vac ~170 vac ~5 v ~1.25 v ~1.25 v ~0.8 v v off v e v in v off(max) pi-6864-050313 figure 9a shows the typical half-line frequency profle of the device switching frequency as a function of input voltage at peak load conditions. figure 9b shows for a given line condition the effect of ecosmart? to the switching frequency as a function of load. the switching frequency is not a function of boost choke inductance in ccm (continuous conduction mode) operation. ecosmart the hiperpfs-2 includes an ecosmart mode wherein the internal error signal (v e ) is used to detect the converter output power. since the internal error-signal is proportional to the output power, this signal level is used to set the average switching frequency as a function of output power. the off-time integrator control reference (v off ) is controlled with respect to the internal error-voltage level (output power) to allow the converter to maintain output voltage regulation and relatively fat conversion effciency between 20% to 100% of rated load
rev. b 06/13 8 pfs7323-7329 www.powerint.com which is essential to meet many effciency directives. the degree of frequency slide is also controlled as a function of peak input line voltage, at high input line the maximum off-time voltage reference at zero error-voltage will be approximately 1/4 of the maximum value at low input line conditions. the lower v off slope reduces the average frequency swing for high input line operation. burst-mode for no-load power consumption reduction unlike the original hiperpfs which had the ability to reduce the minimum on-time to zero, the minimum on-time in hiperpfs-2 has a minimum value of 500 ns to enable burst-mode operation at no-load. since the minimum on-time is 500 ns, at no-load the output voltage will climb until the device shuts off due to the voltage on the compensation pin reaching the c ov threshold. the output voltage ripple at no-load to light load will be increased as a result of the burst-mode operation. a higher minimum on-time and inclusion of the c ov comparator are the main elements in the design to enable this burst-mode operation at no-load. the burst-mode was added to reduce the power stage no-load consumption to below 0.5 w when the boost converter is designed with a ferrite boost choke. power good signal (pg) the hiperpfs-2 features a power good (pg) circuit which comprises of an internal comparator that at start-up turns on a switch when the sensed output voltage on the feedback pin rises to ~95% (v pg(h) threshold) of the set output voltage threshold. during start-up prior to the output voltage reaching v pg(h) the pg signal is in a high-impedance state (internal switch is in off state). when the ac input voltage is removed or other fault occurs after start-up, the power good signal transitions from on to off state once the sensed output voltage on the feedback pin falls to a user selected threshold programmed with a resistor on the power good threshold pin. the power good threshold pin has a fxed source current of i pgt and this combined with the power good threshold resistor sets the figure 11. power good function description. threshold when the power good signal transitions from the on state to the high-impedance high-state as the pfc output voltage falls out of regulation. the power good threshold pin has an internal 100 m s de-glitch flter (t pg ) to prevent noise events from falsely setting the v pg(l) threshold. in the event a load fault prevents the boost from achieving regulation (~95% of the set output voltage threshold) the pg function will remain in the high-impedance state and will not annunciate when a output voltage has fallen below the user programmed v pg(l) threshold. the v pg(l) user programmed threshold is enabled once v pg(h) threshold has been reached. if the pgt programming resistor is left open, the power good function is disabled and remains in the high-impedance (off) state, whereas if the power good threshold pin is shorted to the ground pin the power good signal will remain in the low (on) state until the pfc output voltage has fallen to the c uv threshold. similar to the condition described above, if the value of the pgt resistor is such that the v pg(l) threshold is greater than the v pg(h) threshold the pg signal will remain in the high-impedance off- state. power good function is not valid under the following conditions: a. vcc is not in a valid range. below v cc- , the power good function is not valid. b. reference pin resistor is in an invalid range. if the reference pin resistor is not either 24. 9 k w for full or 49.9 k w for effciency mode, the power good signal is not valid. power good will go to high-impedance state (internal mosfet is off) at the end of the fast soft-shutdown initiated by the reference pin resistor fault. c. the valid programming range of pgt is between 275 v to 360 v. programming an output voltage below 275 vdc to trigger pg is invalid. output voltage rising output voltage falling t pg t pg pg = high impedance pg = high impedance pg = on-state set internally by v pg(h) 95% v out (361 v) 100% v out (380 v) 87.5% v out (333 v) set externally by r pg . . r i v a v k 08 75 50 52 5 105 pg pg ref # n x == = pi-6700-040512
rev. b 06/13 9 pfs7323-7329 www.powerint.com figure 12. reference pin current operating range. d. once the start-up sequence check has passed and the converter goes into soft-start and if pgt is shorted to signal ground pin, then the pg signal will toggle to the low state (internal mosfet is on) when the output voltage reaches 85-100% of the set regulation threshold and will remain in this state until the output voltage reaches zero volt or conditions in a, b or c occur. e. once the start-up sequence check has passed and the converter goes into soft-start and if pgt is open, then the pg signal will remain in the high-impedance state (internal mosfet is off). reference and selectable power limit besides the internal current reference source, the precision resistor on the reference pin also allows user selection between full and effciency power limit for each device. the effciency power mode will permit user selection of a larger device for a given output power requirement for increased conversion effciency. in full power mode the reference pin resistor is 24.9 k w 1% and the effciency power limit mode is selected with a 49.9 k w 1% resistor. if the reference pin is shorted (to ground pin) or open circuited the ic will initiate a fast soft-shutdown and disable the power mosfet and remain disabled until all the conditions for the start-up sequence are satisfed. the reference pin resistor value and power mode is latched at start-up. protection modes voltage monitor (v) pin shutdown the voltage monitor pin features a shutdown protection mode which can be used with the voltage monitor pin resistor or external circuitry to cover system faults. during start-up (1 v < vfb < 5.8 v) in the event the current through the voltage monitor pin exceeds the i v(off) threshold for a duration exceeding approximately (1 m s), the ic disables the internal mosfet for the entire duration that the voltage monitor pin current is above i v(off) . in normal operation, if the current through the voltage monitor pin exceeds the i v(off) threshold for a duration exceeding t v(off) , the ic will re-initiate the start-up sequence. brown-in protection (i uv+ ) the voltage monitor pin features an input line undervoltage detection to limit the minimum start-up voltage detected through the voltage monitor pin. this detection threshold will inhibit the device from starting at very low input ac voltage. brown-out protection (i uv- ) the voltage monitor pin features a brown-out protection mode wherein the hiperpfs will turn-off when the voltage monitor pin current is below the line uv- threshold (i uv- ) for a period exceeding the t brown-out time period. in the event a single half-line cycle is missing (normal operating line frequency is 47 to 63 hz) the brown-out protection will not be activated. the hiperpfs-2 soft-shutdown in effect gradually reduces the internal error-voltage to zero volts at rate of 1 v/ms to decay the power mosfet on-time to zero. at peak power (v e ~5 v) the shutdown time will be approximately 5 ms. the internal error-voltage is held at 0 v for as long as the input peak voltage is below the brown-in (i uv+ ) threshold. the internal error-voltage controlled slew to 0 v gradually reduces the switch on-time to zero to deplete energy stored in the boost choke as well as input emi flter for power-down. once the error-voltage reaches zero volts the controller is effectively in an off-state (gated by 5 ms timer) and will restart once all the conditions of soft-start are satisfed. at start-up and during soft-start the brown-out threshold (same as line uv-) is reduced to i uv(ss) and brown-out timer is also extended to t uv(ss) (soft-start brown-out timer). soft-start brown-out threshold (i uv(ss) ) is reset to i uv- once the internal error-voltage has begun to fall (indicating the converter has reached steady-state output voltage regulation). the soft-start brown-out timer is reset to the normal brown-out timer once the internal error-voltage has begun to fall (indicating the converter has reached steady-state output voltage regulation) and the voltage monitor pin current exceeds i uv- . if the voltage monitor pin current is still below the i uv(ss) threshold after the end of the soft-start brown-out timer (t uv(ss) ), then the converter will fail to start and initiate a soft-shutdown followed by a soft start-up sequence as described in fowchart in figure 8. pi-6863-050313 i ocp ~170 vac v in ~140 vac i v < ~48 a i v > ~59 a figure 13. line dependent ocp. pi-6701-030212 normal range for ?efficiency mode? r = 49.9 k normal range for ?full mode? r = 24.9 k 30 a 20 a 25 a 50 a 40 a 60 a ic-off ic-off ic-off
rev. b 06/13 10 pfs7323-7329 www.powerint.com temporarily reducing the brown-out threshold prevents false turn-off at high power start-up when voltage drop across the input bridge rectifer and flter stage may cause the rectifed input to sag below the brown-out threshold. increasing the brown-out timer during soft-start permits a longer time for an in-line ac-side ntc to reduce its resistance and increase the voltage presented to the voltage monitor pin. in the event the converter does not reach regulation at start-up (overload or power limit condition) c uv protection threshold is not activated and both the i uv(ss) and t uv(ss) are not reset. it is expected that while the input voltage peak is below the brown-out threshold (i uv- ) during a line cycle drop out or line sag event the internal peak detector will force refresh the line feed-forward gain (m on ) to the minimum value at the t refresh sample rate. similar to the original hiperpfs, the controller latches the ocp threshold in the event of an ac line cycle drop-out when the peak sense is for a high input line condition (v in > 170 vac). fast output voltage overvoltage protection (fb ov ) this family features a feedback pin that is connected directly to the output voltage resistor divider network to permit fast feedback information to the controller for fast load transient response. the compensation pin which is also connected to the voltage divider network includes a resistor to isolate the slow feedback path and loop compensation network into the controller for steady-state output voltage regulation. comparators on the feeback and compensation pins are used to verify that the pins are not open-circuited and that the main voltage divider voltage at start-up is greater than fb off and c off in order to complete the start-up fault detect sequence. after start-up the fb off and c off thresholds remain enabled. similarly to the original hiperpfs, this controller includes internal fb ov (feedback pin overvoltage), c ov (compensation pin overvoltage) and c uv (compensation pin undervoltage) protection thresholds that are detected through the feedback and compensation pins. deglitch flters (t fb(ov) and t c(uv) ) are also used to prevent the controller from falsely triggering this protection mode. a fb ov event in excess of the t fb(ov) delay will terminate the switch cycle immediately. the compensation pin also features an output voltage undervoltage detection threshold to detect an overload or open-loop condition (broken feedback). in the event the falling edge of the voltage on the compensation pin falls below the c uv threshold, the mosfet is disabled and the soft-start start-up sequence is initiated. the compensation pin undervoltage protection (c uv ) mode is disabled during start-up and enabled once the compensation pin voltage exceeds approximately 5.8 v. the brown-out threshold is also reset from i uv(ss) to i uv- under the same conditions as activation of the c uv threshold. vcc undervoltage protection (uvlo) the bias power (vcc) pin has an undervoltage lock-out protection which inhibits the ic from starting unless the applied vcc voltage is above the vcc+ threshold. the ic initiates a soft-start once the vcc pin voltage exceeds the vcc+ threshold. after start-up the ic will continue to operate until the vcc pin voltage has fallen below vcc- level. the absolute maximum voltage of the vcc pin is 15 v which must be externally limited to prevent damage to the ic. over-current protection the device includes a cycle-by-cycle over-current-protection (ocp) mode which protects the device in the event of a catastrophic fault. the ocp mode in the hiperpfs-2 is input line dependent as shown in figure 13. the intention of ocp in this device is strictly protection of the internal power mosfet and is not intended to protect the converter from output short-circuit or overload fault conditions. the hiperpfs-2 latches the high input line ocp for a 1/2 line cycle and updates the ocp status after the expiration of a 5 ms block-out timer. this feature has particular beneft for hard-start after an ac line cycle drop where the peak detector may falsely detect a low input line condition even though the input is at high input line. a leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time is set so that current spikes caused by capacitance and rectifer reverse recovery time will not cause premature termination of the mosfet conduction. safe operating area (soa) mode since the cycle-by-cycle ocp mechanism described above does not prevent the possibility of inductor current stair-casing, an soa mode is also featured. rapid buildup of the device current can occur in the event of inductor saturation or when the input and output voltages are equal (no or very short inductor reset time). the soa mode is triggered whenever the device reaches current limit (i ocp ) and the on-time is less than t soa . the soa mode forces an off-time equal to t ocp and pulls the internal error-voltage (v e ) down to approximately 1/2 of its set value. open feedback pin protection the feedback pin also features a static current of i fb that is continuously sourced out of the pin to protect against a fault related to an open feedback pin. the internal current source introduces a static offset to the output regulation which must be accounted for in selecting the output feedback regulation components.
rev. b 06/13 11 pfs7323-7329 www.powerint.com output power table esip package product effciency power mode r = 49.9 k w full power mode r = 24.9 k w maximum continuous output power rating at 90 vac 2 peak output power rating at 90 vac 4 maximum continuous output power rating at 90 vac 2 peak output power rating at 90 vac 4 minimum 3 maximum minimum 3 maximum pfs7323l 60 w 80 w 90 w 85 w 110 w 120 w PFS7324L 80 w 110 w 120 w 100 w 130 w 150 w pfs7325l 110 w 150 w 165 w 140 w 185 w 205 w pfs7326h 140 w 185 w 205 w 180 w 230 w 260 w pfs7327h 175 w 230 w 255 w 220 w 290 w 320 w pfs7328h 210 w 280 w 310 w 270 w 350 w 385 w pfs7329h 235 w 320 w 345 w 293 w 380 w 425 w table 2. output power table. notes: 1. see key application considerations. 2. maximum practical continuous power at 90 vac in an open-frame design with adequate heat sinking, measured at 50 c ambient. 3. recommended lower range of maximum continuous power for best light load effciency ; hiperpfs-2 will operate and perform below this level. 4. internal output power limit. hysteretic thermal shutdown the thermal shutdown circuitry senses the controller die temperature. the threshold is set at 117 c typical with a 49 c hysteresis. when the die temperature rises above this threshold (otp) (117 c +8/-7 c), the controller initiates a fast soft- shutdown and remains disabled until the die temperature falls by ~49c, at which point the device will re-initiate the soft-start sequence. in the event an otp is detected when the voltage monitor pin current is below i uv+ threshold, the device will initiate a soft-shutdown and remain disabled until all the conditions for the start-up (soft-start sequence) are satisfed. in this mode of operation the otp hysteresis is disabled. when soft-shutdown is initiated by an over-temperature fault (otp) the brown-out timer delay (t brown-out ) is disabled. the behavior of otp depends on the input voltage peak detected following the thermal fault. if the input peak voltage detected after the thermal fault is below i uv+ , otp hysteresis is disabled, however if the peak input voltage after the thermal fault is above i uv+ then the otp hysteresis is enabled prior to re-initiating the soft-start sequence. the maximum time delay for soft-shutdown to occur after an otp event is detected is t refresh . in the event the input voltage is reduced below the brown-in threshold and an otp event occurs (no otp hysteresis) and the input voltage is raised immediately above brown-in before the controller junction temperature falls below the otp threshold, the controller will initiate a soft-start once the controller junction is just below the otp threshold. depending on the system thermal conditions, the controller could initiate otp shutdown again because of insuffcient time to cool down the controller. the otp shutdown that occurs when the input voltage is above brown-in will have hysteresis enabled.
rev. b 06/13 12 pfs7323-7329 www.powerint.com application example a high effciency, 350 w, 385 vdc universal input pfc the circuit shown in figure 14 is designed using a pfs7328h device from the hiperpfs-2 family of integrated pfc controllers. this design is rated for a continuous output power of 350 w and provides a regulated output voltage of 385 vdc nominal maintaining a high input power factor and overall effciency from light load to full load. fuse f1 provides protection to the circuit and isolates it from the ac supply in case of a fault. diode bridge br1 rectifes the ac input. capacitors c1, c2, c3, and c4 together with inductors l1, l2, and l3 form the emi flter reducing the common mode and differential mode noise. resistors r1, r2 and capzero, ic u2 are required to discharge the emi flter capacitors once the circuit is disconnected. capzero eliminates static losses in r1 and r2 by only connecting these components across the input when ac is removed. the boost converter stage consists of inductor l5, and the hiperpfs-2 ic u1. this converter stage works as a boost converter and controls the input current of the power supply while simultaneously regulating the output dc voltage. diode d3 prevents a resonant build up of output voltage at start-up by bypassing inductor l5 while simultaneously charging output capacitor c13. thermistor rt1 limits the inrush input current of the circuit at start-up and prevents saturation of l5. in most high-performance designs, a relay will be used to bypass the thermistor after start-up to improve power supply effciency. capacitor c10 is used for reducing the loop length and area of the output circuit to reduce emi and overshoot of voltage across the drain and source of the mosfet inside u1 at each switching instant. the pfs7328h ic requires a regulated supply of 12 v for operation and must not exceed 15 v. resistors r10, r11, r12, zener diode vr1, and transistor q2 form a series pass regulator that prevents the supply voltage to ic u1 from exceeding 12 v. capacitors c6, and c9 flter the supply voltage and provide decoupling to ensure reliable operation of ic u1. diode d5 provides reverse polarity protection. resistor r15 programs the output voltage level [via the power good threshold (pgt) pin] below which the power good [pg] pin will go into a high-impedance state. ic u1 is confgured in full power mode by resistor r14. capacitor c8 decouples reference pin of ic u1. the rectifed ac input voltage of the power supply is sensed by ic u1 using resistors r7, r8 and r9. the capacitor c7 flters any noise on this signal. divider network comprising of resistors r18, r19, r20, and r21 are used to scale the output voltage and provide feedback to ic u1. capacitor c14 enables rapid correction of output voltage overshoot or undershoot resulting from transient loading. resistor r17, r16, and capacitors c12 and c11 are required for shaping the loop response of the feedback network. the combination of resistor r16 and capacitor c12 provide a low frequency zero and the resistor r17, r16 and capacitor c12 form a low frequency pole. c15 and r22 attenuate high- frequency noise. diode d6 protects against an accidentally shorted capacitor c12 by safely shutting down the ic. figure 14. 350 w pfc using pfs7328h. l5 360 h v o dc out + v o s c pgt fb vcc pg k d r g v control hiperpfs-2 u1 pfs7328h pi-6971-041713 n remote on e l r1 220 k? rt1 2.5 ? r10 1 ? 1% r5 16 k? r6 3 k? d2 d1 s1ab r4 10 k? d4 bav16 c6 47 f 50 v c5 1 f 450 v c7 22 nf 50 v r14 24.9 k? 1% r15 100 k? 1% r16 7.5 k? 1% r17 487 ? c8 470 pf 50 v d5 s1ab vr1 1n4743a 13 v q1 mmbt4403 3 4 2 1 u3 ltv817a q2 mmbt4401lt1g r11 1 ? 1% r12 2.2 k? 1% r2 220 k? r3 10 ? 2 w 1% l1 ferrite bead br1 gbu8k-bp 800 v l2 9 mh c2 220 nf 275 v c4 680 pf 250 vac c3 680 pf 250 vac c1 680 nf 275 vac f1 6.3 a rv1 320 vac auxiliary power supply t o d1 capzero u2 cap005dg d2 l3 220 h + + c12 2.2 f 25 v c13 270 f 450 v c14 47 nf 200 v r21 60.4 k? 1% r18 1.5 m? 1% r7 1.5 m? 1% r8 1.5 m? 1% r9 1 m? 1% r19 787 k? r20 1.6 m? 1% c10 10 nf 1 kv c11 22 nf 25 v d6 bav116 d3 1n5408-t c9 3.3 f 25 v r22 3 k? c15 47 nf 25 v
rev. b 06/13 13 pfs7323-7329 www.powerint.com design, assembly, and layout considerations power table the data sheet power table as shown in table 2 represents the maximum practical continuous output power based on the following conditions: for the universal input devices (pfs7323l-pfs7329h): 1. an input voltage range of 90 vac to 264 vac. 2. overall effciency of at least 93% at the lowest operating voltage. 3. 385 v nominal output. 4. suffcient heat sinking to keep device temperature 100 oc. operation beyond the limits stated above will require derating. use of a nominal output voltage higher than 390 v is not recommended for hiperpfs-2 based designs. operation at voltages higher than 390 v can result in higher than expected drain-source voltage during line and load transients. hiperpfs-2 selection selection of the optimum hiperpfs-2 part depends on required maximum output power, pfc effciency and overall system effciency (when used with a second stage dc-dc converter), heat sinking constraints, system requirements and cost goals. the hiperpfs-2 part used in a design can be easily replaced with the next higher or lower part in the power table to optimize performance, improve effciency or for applications where there are thermal design constraints. minor adjustments to the inductance value and emi flter components may be necessary in some designs when the next higher or the next lower hiperpfs-2 part is used in an existing design for performance optimization. every hiperpfs-2 family part has an optimal load level where it offers the most value. operating frequency of a part will change depending on load level. change of frequency will result in change in peak-to-peak current ripple in the inductance used. change in current ripple will affect input pf and total harmonic distortion of input current. input fuse and protection circuit the input fuse should be rated for a continuous current above the input current at which the pfc turns-off due to input under voltage. this voltage is referred to as the brown-out voltage. the fuse should also have suffcient i 2 t rating in order to avoid nuisance failures during start-up. at start a large current is drawn from the input as the output capacitor charges to the peak of the applied voltage. the charging current is only limited by any inrush limiting thermistors, impedance of the emi flter inductors, esr of output capacitor and the forward resistance of the input rectifer diodes. a mov will typically be required to protect the pfc from line surges. selection of the mov rating will depend on the energy level (en1000-4-5 class level) to which the pfc is required to withstand. a suitable ntc thermistor should be used on the input side to provide inrush current limiting. choice of this thermistor should be made depending on the inrush current specifcation for the power supply. ntc thermistors may not be placed in any other location in the circuit as they fail to limit the stress on the part in the event of line transients and also fail to limit the inrush current in a predictable manner. example shown in figure 14 shows the circuit confguration that has the inrush limiting ntc thermistor on the input side which is bypassed with a relay after pfc start-up. this arrangement ensures that a consistent inrush limiting performance is achieved by the circuit. input emi filter the variable switching frequency of the hiperpfs-2 effectively modulates the switching frequency and reduces conducted emi peaks associated with the harmonics of the fundamental switching frequency. this is particularly benefcial for the average detection mode used in emi measurements. the pfc is a switching converter and will need an emi flter at the input in order to meet the requirements of most safety agency standards for conducted and radiated emi. typically a common mode flter with x capacitors connected across the line will provide the required attenuation of high frequency components of input current to an acceptable level. the leakage reactance of the common mode flter inductor and the x capacitors form a low pass flter. in some designs, additional differential flter inductors may have to be used to supplement the differential inductance of the common mode choke. a flter capacitor with low esr and high ripple current capability should be connected at the output of the input bridge rectifer. this capacitor reduces the generation of the switching frequency components of the input current ripple and simplifes emi flter design. typically, 0.33 m f per 100 w should be used for universal input designs and 0.15 m f per 100 w of output power should be used for 230 vac only designs. it is often possible to use a higher value of capacitance after the bridge rectifer and reduce the x capacitance in the emi flter. regulatory requirements require use of a discharge resistor to be connected across the input (x) capacitance on the ac side of the bridge rectifer. this is to ensure that residual charge is dissipated after the input voltage is removed when the capacitance is higher than 0.1 m f. use of capzero integrated circuits from power integrations, helps eliminate the steady- state losses associated with the use of discharge resistors connected permanently across the x capacitors. inductor design it is recommended that the inductor be designed with the maximum operating fux density less than 0.3 t and a peak fux density less than 0.39 t at maximum current limit when a ferrite core is used. if a core made from sendust or mpp is used, the fux density should not exceed 1 t. a powder core inductor will have a signifcant drop in inductance when the fux density approaches 1 t.
rev. b 06/13 14 pfs7323-7329 www.powerint.com for high performance designs, use of litz wire is recommended to reduce copper loss due to skin effect and proximity effect. for toroidal inductors the numbers of layers should be less than 3 and for bobbin wound inductors, inter layer insulation should be used to minimize inter layer capacitance. for ferrite core inductor, a nominal k p value of 0.35 is recommended for an optimal design. for sendust core inductor, a nominal k p value of 0.6 is recommended for an optimal design. output capacitor for a 385 v nominal pfc, use of a electrolytic capacitor with 450 v or higher continuous rating is recommended. the capacitance required is dependent on the acceptable level of output ripple and any hold-up time requirements. the equations below provide an easy way to determine the required capacitance in order to meet the hold-up time requirement and also to meet the output ripple requirements. the higher of the two values would be required to be used. capacitance required for meeting the hold-up requirement is calculated using the equation: ## 2 vv pt c _ o ou to ut mi n ou th ol du p 22 = - ^h c o pfc output capacitance in f. p o pfc output power in watts. t hold-up hold-up time specifcation for the power supply in seconds. v out lowest nominal output voltage of the pfc in volts. v out(min) lowest permissible output voltage of the pfc at the end of hold-up time in volts. capacitance required for meeting the low frequency ripple specifcation is calculated using the equation: ## # 2 c fv i o ll pf c om ax # rh d = ^h f l input frequency in hz. ? v o peak-peak output voltage ripple in volts. pfc pfc operating effciency. i o(max) maximum output current in amps. capacitance calculated using the above method should be appropriately increased to account for ageing and tolerances. power supply for the ic a 12 v regulated supply should be used for the hiperpfs-2. if the vcc exceeds 15 v, the hiperpfs-2 may be damaged. in most applications a simple series pass linear regulator made using an npn transistor and zener diode is adequate since the hiperpfs-2 only requires approximately 3.4 ma maximum for its operation. it is recommended that a 3.3 m f or higher, low esr ceramic capacitor be used to decouple the vcc supply. this capacitor should be placed directly at the ic on the circuit board. line-sense network the line-sense network connected to the voltage monitor pin provides input voltage information to the hiperpfs-2. the value of this resistance sets the brown-in and brown-out threshold for the part. a value of 4 m w is recommended for use with the universal input parts. only 1% tolerance resistors are recommended. this resistance value may be modifed to adjust the brown-in threshold if required however change of this value will affect the maximum power delivered by the part. a decoupling capacitor of 22 nf is required to be connected from the voltage monitor pin to the ground pin of the hiperpfs-2 for the universal input parts. this capacitor should be placed directly at the ic on the circuit board. feedback network a resistor divider network that provides 6 v at the feedback pin at the rated output voltage should be used. the compensation elements are included with the feedback divider network since the hiperpfs-2 does not have a separate pin for compensation. the hiperpfs-2 based pfc has two loops in its feedback. it has an inner current loop and a low bandwidth outer voltage loop which ensures high input power factor. the compensation rc circuit included with the feedback network reduces the response time of the hiperpfs-2 to fast changes in output voltage resulting from transient loads. the recommended circuit and the associated component values are shown in figure 15. resistors r1 to r4 comprise of the main output voltage divider network. the sum of resistors r1, r2 and r3 is the upper divider resistor and the lower feedback resistor is r4. capacitor c1 is a soft-fnish capacitor that reduces output voltage overshoot at start-up. capacitor c c is to flter any switching noise from coupling into the compensation pin. resistor r7 and capacitor c3 is the loop compensation network which figure 15. recommended feedback circuit. pi-6989-041813 s c pgt fb vcc pg b + r2 r4 r6 r7 c c d1 c r c3 r r c1 r1 r3 r5 c2 k d r g v control hiperpfs-2
rev. b 06/13 15 pfs7323-7329 www.powerint.com introduces a low frequency zero required to tailor the loop response to ensure low cross-over frequency and suffcient phase margin. resistor r6 isolates the fast portion (resistor voltage divider network comprising of resistors r1 to r4) and the slow feedback loop compensator circuit (resistor r7 and capacitor c3). diode d1 is included to cover a single point fault condition wherein capacitor c3 is shorted. in the event c3 is short-circuited, the feedback pin is forced below the fb off threshold through diode d1 and subsequently turns the hiperpfs-2 off. only a standard recovery diode should be used for d1. use of ultrafast or fast recovery diode is not recommended including small signal diodes (e.g. 1n4148), which are typically also fast recovery. the recommended values for the components used are as follows: r4 = 60.4 k w r3 = 1.6 m w r2 = 787 k w c1 = 47nf, 200 v x7r/npo r6 = 487 k w r7 = 7.5 k w c3 = 2.2 m f cc = 22 nf d1 = bav116 w or 1n4007 (a general purpose standard recovery diode should only be used). when the above component values are used, the value of resistor r1 can be calculated using the following equation: figure 16. heat sink assembly C using thermally conductive adhesive. r v r 10 01 0 75 o 1 6 3 # = - - - the value of resistor r7 will have to be adjusted in some designs and as a guideline the value from the following calculation can be used: ## . rr vc p k 12 z oo o 7 2 x == ^h p o maximum continuous output power in watts v o nominal pfc output voltage in volts c o pfc output capacitance in farads improvement in low frequency phase margin can be achieved by increasing the value of the capacitor c3 however increase in value of capacitor c3 will result in some increase in overshoot at the output of the pfc during transient loading and should be verifed. heat sinking and thermal design figure 16, 17, 18 shows examples of the recommended assembly for the hiperpfs-2. in these assemblies as shown, no insulation pad is required and hiperpfs-2 can be directly connected to heat sink by clip or adhesive thermal material. the hiperpfs-2 back metal is electrically connected to the heat sink and the heat sink is required to be connected to the hiperpfs-2 source terminal in order to reduce emi.
rev. b 06/13 16 pfs7323-7329 www.powerint.com figure 17. heat sink assembly C with metal clip. figure 18. heat sink assembly C with plastic clip.
rev. b 06/13 17 pfs7323-7329 www.powerint.com pcb design guidelines and design example the line-sense network and the feedback circuit use large resistance values in order to minimize power dissipation in the feedback network and the line-sense network. care should be taken to place the feedback circuit and the line-sense network components away from the high-voltage and high current nodes to minimize any interference. any noise injected in the feedback network or the line-sense network will typically manifest as degradation of power factor. excessive noise injection can lead to waveform instability or dissymmetry. the emi flter components should be clustered together to improve flter effectiveness. the placement of the emi flter components on the circuit board should be such that the input circuit is located away from the drain node of the, or the pfc inductor. a flter or decoupling capacitor should be placed at the output of the bridge rectifer. this capacitor together with the x capa- figure 19. pcb layout example for system power supply consisting of a pfc and a second stage converter. citance in the emi flter and the differential inductance of the emi flter section and the source impedance, works as a flter to reduce the switching frequency current ripple in the input current. this capacitor also helps to minimize the loop area of the switching frequency current loop thereby reducing emi. the connection between the hiperpfs-2 drain node, output diode drain terminal and the pfc inductor should be kept as small as possible. a low-loss ceramic dielectric capacitor should be connected between the cathode of the pfc output diode and the source terminal of the hiperpfs-2. this ensures that the loop area of the loop carrying high frequency currents at the transition of switch-off of the mosfet is small and helps to reduce radiated emi due to high frequency pulsating nature of the diode current traversing through the loop. pfc output emi filter thermistor shorting relay bridge rectier pfc inductor hiperpfs auxiliary supply for pfc ? from standby power supply input capacitor pfc output capacitor pi-7010-042313 ac input
rev. b 06/13 18 pfs7323-7329 www.powerint.com during placement of components on the board, it is best to place the voltage monitor pin, feedback pin and vcc pin decoupling capacitors close to the hiperpfs-2 before the other components are placed and routed. power supply return trace from the ground pin should be separate from the trace connecting the feedback circuit components to the ground pin. to minimize effect of trace impedance affecting regulation, output feedback should be taken directly from the output capacitor positive terminal. the upper end of the line-sense resistors should be connected to the high frequency flter capacitor connected at the output of the bridge rectifer. quick design checklist as with any power supply design, all hiperpfs-2 designs should be verifed on the bench to make sure that component specifcations are not exceeded under worst-case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that peak vds does not exceed 530 v at lowest input voltage and maximum overload output power. maximum overload output power occurs when the output is overloaded to a level just above the highest rated load or before the power supply output voltage starts falling out of regulation. additional external snubbers should be used if this voltage is exceeded. in most designs, addition of a ceramic capacitor in the range of 33 pf and 100 pf connected across the pfc output diode will reduce the maximum drain-source voltage to a level below the bvdss rating. when measuring drain-source voltage of the mosfet, a high voltage probe should be used. when the probe tip is removed, a silver ring in the vicinity of the probe tip can be seen. this ring is at ground potential and the best ground connection point for making noise free measurements. wrapping stiff wire around the ground ring and then connecting that ground wire into the circuit with the shortest possible wire length, and connecting the probe tip to the point being measured, ensures error-free measurement. probe should be compensated according to probe manufacturers guidelines to ensure error-free measurement. 2. maximum drain current C drain current can be measured indirectly by monitoring inductor current. a current probe should be inserted between the bridge rectifer and inductor connection. at maximum ambient temperature, minimum input voltage and maximum output load, verify inductor current waveforms at start-up for any signs of inductor saturation. when performing this measurement with sendust inductor, it is typical to see inductor waveforms that show exponential increase in current due to permeability drop. this should not be confused with hard saturation. 3. thermal check C at maximum output power, minimum input voltage and maximum ambient temperature; verify that temperature specifcations are not exceeded for the hiperpfs-2, pfc inductor, output diodes and output capacitors. enough thermal margin should be allowed for the part-to-part variation of the rds(on) of hiperpfs-2, as specifed in the data sheet. a maximum package temperature of 100 c under worst-case operating conditions is recommended to allow for these variations. 4. input pf should improve with load, if performance is found to progressively deteriorate with loading then that is a sign of possible noise pickup by the voltage monitor pin circuit or the feedback divider network and the compensation circuit.
rev. b 06/13 19 pfs7323-7329 www.powerint.com parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units control functions maximum operating on-time t on(max) 0 c < t ji < 100 c 30 40 50 m s minimum operating on-time t on(min) 0 c < t ji < 100 c see note a 0.5 1 maximum operating off-time t off(max) 0 c < t ji < 100 c 30 40 50 minimum operating off-time t off(min) 0 c < t ji < 100 c 1 3.5 internal feedback voltage reference v ref t ji = 25 c see note a 5.955 6.00 6.045 v compensation pin voltage v c 0 c < t ji < 100 c (in regulation) 5.88 6.00 6.12 v feedback pin current i fb t ji = 25 c normal operation 340 500 640 na soft-start time t soft t ji = 25 12 ms internal compensation frequency f comp see note a pole (fp) 1 khz error-amplifer gain a v see note a 100 v/v absolute maximum ratings (2) drain pin peak current: pfs7323 .................................... 7. 5 a pfs7324 .................................... 9.0 a pfs7325 .................................. 11. 3 a pfs7326 .................................. 13.5 a pfs7327 .................................. 15.8 a pfs7328 .................................. 18.0 a pfs7329 .................................. 21.0 a drain pin voltage ............................. -0.3 v to 530 v / 540 v (5) vcc, pg, pgt pin voltage .................................. -0.3 v to 15 v vcc pin current .............................................................. 25 ma voltage monitor pin voltage ................................-0.3 v to 9 v feedback pin voltage .......................................... -0.3 v to 9 v compensation pin voltage ................................ -0.3 v to 9 v reference pin voltage ....................................... -0.3 v to 9 v storage temperature ...................................... ..... -65 c to 150 c junction temperature (3) ................................... -40 c to 150 c lead temperature (4) ........................................................ 260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. maximum ratings specifed may be applied one at a time without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. 3. normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. limited to a duration 15 ns and at a drain current i lim(typ) . thermal resistance thermal resistance: h/l package: ( q ja ) (1) .......................... .......................... 103 c/w ( q jc )................................................ .. (see figure 20) notes: 1. controller junction temperature (t ji ) may be less than the internal power mosfet junction temperature (t j(m) ) and diode junction temperature (t j(d) ). qspeed diode peak repetitive reverse voltage (v rrm ) 530 v average forward current (i f(avg) ) t j(d) = 150 c 3 a non-repetitive peak surge current (i fsm ) 60 hz, ? cycle, t c(d) = 25 c 50 a non-repetitive peak surge current (i fsm ) 500 m s, t c(d) = 25 c 130 a
rev. b 06/13 20 pfs7323-7329 www.powerint.com parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units line-sense/peak detector brown-in threshold current i uv+ 0 c < t ji < 100 c 27.50 28.88 m a brown-out threshold current i uv- 0 c < t ji < 100 c 22.52 24.50 m a brown-in/out hysteresis i uv(hyst) 0 c < t ji < 100 c 2.5 5.5 m a soft-start brown-out threshold current i uv(ss) t ji = 25 c 20.62 m a soft-start brown-out time-out t uv(ss) t ji = 25 c 1000 ms voltage monitor pin voltage threshold v v(thr) 0 c < t ji < 100 c i v = i uv+ 1.6 2.3 3.1 v voltage monitor pin short-circuit current i v(sc) 0 c < t ji < 100 c v v = 6 v 280 m a voltage monitor pin pre-soft-start current i v(ss) 0 c < t ji < 100 c v v = 3 v 5 ma line sample refresh period t refresh t ji = 25 c 16 60 ms brown-out timer t brown-out t ji = 25 c 32 60 ms voltage monitor pin shutdown current threshold i v(off) 0 c < t ji < 100 c 200 m a voltage monitor pin shutdown delay t v(off) t ji = 25 c 65 110 135 m s
rev. b 06/13 21 pfs7323-7329 www.powerint.com parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units current limit/circuit protection over-current protection i ocp pfs7323l di/dt = 250 ma/ m s t ji = 25 c i v < 48 m a 3.8 4.1 4.3 i v > 59 m a 2.5 2.9 3.2 PFS7324L di/dt = 300 ma/ m s t ji = 25 c i v < 48 m a 4.5 4.8 5.1 i v > 59 m a 3.0 3.5 3.8 pfs7325l di/dt = 400 ma/ m s t ji = 25 c i v < 48 m a 5.5 5.9 6.2 i v > 59 m a 3.7 4.2 4.7 pfs7326h di/dt = 500 ma/ m s t ji = 25 c i v < 48 m a 6.8 7.2 7.5 i v > 59 m a 4.6 5.2 5.7 pfs7327h di/dt = 650 ma/ m s t ji = 25 c i v < 48 m a 8.0 8.4 8.8 i v > 59 m a 5.4 6.0 6.6 pfs7328h di/dt = 800 ma/ m s t ji = 25 c i v < 48 m a 9.0 9.5 9.9 i v > 59 m a 6.0 6.6 7.3 pfs7329h di/dt = 920 ma/ m s t ji = 25 c i v < 48 m a 10.0 10.5 11.0 i v > 59 m a 6.6 7.4 7.9 soa protection time-out t ocp t ji = 25 c 265 315 365 m s soa on-time t soa t ji = 25 c see note a 1 m s leading edge blanking (leb) time t leb see note a 220 ns current limit delay (ild) t il(d) see note a 100 ns leb + ild + driver delay t leb + t il(d) + t driver t ji = 25 c 370 470 570 ns thermal shutdown temperature t shut see note a 110 117 125 c thermal shutdown hysteresis t hyst see note a 49 c compensation pin undervoltage threshold c uv t ji = 25 c 3 3.5 4 v compensation pin undervoltage delay t c(uv) t ji = 25 c 65 100 135 m s feedback start-up threshold fb off 0 c < t ji < 100 c 1.15 1.25 1.45 v feedback pin off delay t fb(off) 0 c < t ji < 100 c 5 m s
rev. b 06/13 22 pfs7323-7329 www.powerint.com parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units current limit/circuit protection (cont.) compensation pin start-up threshold c off 0 c < t ji < 100 c 0.5 1.2 1.65 v compensation pin off delay t c(off) 0 c < t ji < 100 c 5 m s feedback pin overvoltage threshold fb ov 0 c < t ji < 100 c referenced to v ref v ref +600 mv v ref +700 mv v ref +850 mv v compensation pin overvoltage threshold c ov 0 c < t ji < 100 c referenced to v ref v ref +25 mv v ref +90 mv v ref +160 mv v 0 c < t ji < 100 c hysterisis 50 mv feedback pin/ compensation pin overvoltage delay t fb(ov) t c(ov) 0 c < t ji < 100 c 1 2 3 m s feedback pin overvoltage hysteresis fb ov(hyst) 0 c < t ji < 100 c +300 mv v feedback pin overvoltage offset threshold fbc ov 0 c < t ji < 100 c referenced to v c (compensation pin) v c +225 mv v c +250 mv v c +275 mv v feedback pin undervoltage offset threshold fbc uv 0 c < t ji < 100 c referenced to v c (compensation pin) v c -275 mv v c -250 mv v c -215 mv v feedback pin charge current i fbc 0 c < t ji < 100 c | v fb -v c | > 215 mv 2 ma start-up v cc (rising edge) v cc+ t ji = 25 c 9.5 10.2 v vcc operating range v cc t ji = 25 c, see note a 10.2 12 13.2 v shutdown v cc (falling edge) v cc- t ji = 25 c 9.0 9.5 v vcc hysteresis vcc (hyst) 0 c < t ji < 100 c 0.2 0.5 0.8 v supply current characteristics i cd1 0 c < t ji < 100 c switching 3.5 ma i cd2 0 c < t ji < 100 c not switching 2.5 vcc power-up reset threshold v cc(por) t ji = 25 c 2.85 3.6 4.25 v vcc power-up reset current i vcc(por) t ji = 25 c 2.5 ma reference pin voltage v r 0 c < t ji < 100 c r ref = 24.9 k w 1.240 1.265 1.300 v reference pin threshold i r 0 c < t ji < 100 c full power mode (24.9 k w ) 48.50 51.00 53.50 m a effciency power mode (49.9 k w ) 24.00 25.50 27.00
rev. b 06/13 23 pfs7323-7329 www.powerint.com parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units current limit/circuit protection (cont.) reference pin off-state current threshold i r(off) t ji = 25 c see figure 12 short reference pin to g/s 60 m a open reference pin 20 power good power good threshold set reference current i pgt 0 c < t ji < 100 c 48.5 51.0 53.5 m a power good delay time t pg t ji = 25 c 100 m s power good internal reference threshold (start-up threshold) v pg(h) 0 c < t ji < 100 c reference to v ref v ref -600 mv v ref -300 mv v ref -0 mv v power good pin leakage current in off-state i pg(off) t ji = 25 c v pgt < v ref C 0.3 v 500 na power good on-state voltage v pg(on) t ji = 25 c i pg = 2 ma 2 v power good comparator input offset voltage v pg(os) 0 c < t ji < 100 c -50 +50 mv power good threshold operating voltage v pgt 0 c < t ji < 100 c see note a 0 13.2 v power good operating voltage v pg 0 c < t ji < 100 c see note a 0 13.2 v power mosfet on-state resistance r ds(on) i d = i ocp 0.5 and i v < 48 m a pfs7323 t j(m) = 25 c 0.58 0.69 w t j(m) = 100 c 1.10 pfs7324 t j(m) = 25 c 0.49 0.58 t j(m) = 100 c 0.92 pfs7325 t j(m) = 25 c 0.39 0.46 t j(m) = 100 c 0.73 pfs7326 t j(m) = 25 c 0.33 0.39 t j(m) = 100 c 0.62 pfs7327 t j(m) = 25 c 0.28 0.33 t j(m) = 100 c 0.52 pfs7328 t j(m) = 25 c 0.25 0.29 t j(m) = 100 c 0.46 pfs7329 t j(m) = 25 c 0.21 0.25 t j(m) = 100 c 0.40
rev. b 06/13 24 pfs7323-7329 www.powerint.com parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units power mosfet (cont.) effective output capacitance c oss t j(m) = 25 c v gs = 0 v, v ds = 0 to 80% v dss (see note a) pfs7323 176 pf pfs7324 210 pfs7325 265 pfs7326 312 pfs7327 320 pfs7328 420 pfs7329 487 breakdown voltage bv dss t j(m) = 25 c, vcc = 12 v i d = 250 m a, v fb = v v = v c = 0 v 530 v breakdown voltage temperature coeffcient bv dss(tc) 0.048 %/ c off-state drain current leakage i dss t j(m) = 100 c v ds = 80% bv dss vcc = 12 v v fb =v v =v c =0 pfs7323 t j(m) = 100 c 80 m a pfs7324 t j(m) = 100 c 100 pfs7325 t j(m) = 100 c 120 pfs7326 t j(m) = 100 c 150 pfs7327 t j(m) = 100 c 170 pfs7328 t j(m) = 100 c 200 pfs7329 t j(m) = 100 c 235 turn-off voltage rise time t r see notes a, b, c 50 ns turn-on voltage fall time t f 100 start-up time delay t start-delay 0 c < t ji < 100 c see note a, b 2 6 10 ms
rev. b 06/13 25 pfs7323-7329 www.powerint.com notes: a. not tested parameter. guaranteed by design. b. tested in typical boost pfc application circuit with 22 nf capacitor between voltage monitor and signal ground pins, and 4 m w resistor from rectifed line to the voltage monitor pin. c. normally limited by internal circuitry. parameter symbol conditions source = 0 v; v cc = 12 v, t ji = -40 c to 125 c (note c) (unless otherwise specifed) min typ max units qspeed diode dc characteristics reverse current i r(d) v r = 530 v, t j(d) = 25 c 0.4 m a v r = 530 v, t j(d) = 100 c 0.07 ma forward voltage v f i f = 3 a, t j(d) = 25 c 1.55 v i f = 3 a, t j(d) = 100 c 1.47 junction capacitance c j v r = 10 v, 1 mhz 18 pf dynamic characteristics reverse recovery time t rr di/dt = 200 a/ m s, vr = 400 v if = 3 a t j(d) = 25 c 25 ns t j(d) = 100 c 31 reverse recovery charge q rr di/dt = 200 a/ m s, vr = 400 v if = 3 a t j(d) = 25 c 33.5 nc t j(d) = 100 c 57 maximum reverse recovery current i rrm di/dt = 200 a/ m s, vr = 400 v if = 3 a t j(d) = 25 c 1.9 a t j(d) = 100 c 2.5 softness factor = t b /t a s di/dt = 200 a/ m s, vr = 400 v if = 3 a t j(d) = 25 c 1 - t j(d) = 100 c 0.45
rev. b 06/13 26 pfs7323-7329 www.powerint.com 0 pfs7323 pfs7324 pfs7325 pfs7326 pfs7327 pfs7328 pfs7329 thermal resistance jc (c/w) 3 2.5 2 1.5 1 0.5 0 pi-6992-032813 thermal resistance of internal qspeed diode is = 5.2 c/w for all devices. thermal resistance of internal power mosfet shown below. typical performance characteristics figure 20. thermal resistance ( q jc ).
rev. b 06/13 27 pfs7323-7329 www.powerint.com pi-6972-022713 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold ?ash, tie bar burrs, gate burrs, and interlead ?ash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include interlead ?ash or protrusions. 5. controlling dimensions in inches (mm). 0.628 (15.95) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 10 ref. all around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 0.027 (0.70) 0.023 (0.58) 0.038 (0.97) 0.076 (1.93) 0.118 (3.00) 0.029 dia hole 0.062 dia pad 0.020 (0.50) 0.016 (0.41) ref. detail a 0.118 (3.00) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 13 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 0.290 (7.37) ref. 0.047 (1.19) c 0.038 (0.97) 0.056 (1.42) ref. 1 3 5 6 7 8 9 10 11 13 14 16 0.653 (16.59) 0.647 (16.43) 2 0.325 (8.25) 0.320 (8.13) 2 a b pin 1 i.d. 0.076 (1.93) 0.012 (0.30) ref. 0.207 (5.26) 0.187 (4.75) 13 0.024 (0.61) 0.019 (0.48) 0.010 m 0.25 m c a b 4 3 0.519 (13.18) ref. front view side view back view pcb foot print end view esip-16d (h package) dimensions in inches, (mm). all dimensions are for reference. 4 0.524 (13.31) ref. 0.208 (5.27) ref.
rev. b 06/13 28 pfs7323-7329 www.powerint.com pi-6791-022713 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold ?ash, tie bar burrs, gate burrs, and interlead ?ash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include interlead ?ash or protrusions. 5. controlling dimensions in inches (mm). 0.038 (0.97) 0.076 (1.93) 0.094 (2.40) 0.029 dia hole 0.062 dia pad front view side view back view pcb foot print end view esip-16g (l package) 0.628 (15.95) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 10 ref. all around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) dimensions in inches, (mm). all dimensions are for reference. 0.653 (16.59) 0.647 (16.43) 2 0.325 (8.25) 0.320 (8.13) 2 a b pin 1 i.d. 0.038 (0.97) typ. 9 places 0.056 (1.42) ref. 1 3 1 3 4 6 8 10 13 16 5 7 9 11 14 4 5 6 7 8 9 10 11 13 14 16 c 0.128 (3.26) 0.122 (3.10) 0.081 (2.06) 0.077 (1.96) detail a 0.094 (2.40) 0.047 (1.19) ref. 0.050 (1.26) ref. 0.144 (3.66) ref. 0.290 (7.37) ref. 13 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 0.076 (1.93) typ. 3 pieces 0.173 (4.39) 0.163 (4.14) 0.079 (1.99) 0.069 (1.74) 13 0.024 (0.61) 0.019 (0.48) 0.010 m 0.25 m c a b 4 3 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) r0.012 (0.30) typ., ref. 0.524 (13.31) ref. 0.208 (5.27) ref.
rev. b 06/13 29 pfs7323-7329 www.powerint.com part marking information ? hiperpfs-2 product family ? pfs-2 series number ? package identifer l plastic esip, l bend h plastic esip part ordering information part number option quantity pfs7323l tube 30 PFS7324L tube 30 pfs7325l tube 30 pfs7326h tube 30 pfs7327h tube 30 pfs7328h tube 30 pfs7329h tube 30 pfs 7323 l
revision notes date a initial release. 06/03/13 b updated t brown-out . updated minimum i ocp for pfs7329h. 06/10/13 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, lytswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2013, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany lindwurmstrasse 114 80337 munich germany phone: +49-895-527-39110 fax: +49-895-527-39200 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via milanese 20, 3rd. fl. 20099 sesto san giovanni (mi) italy phone: +39-024-550-8701 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #19-01/05 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei 11493, taiwan r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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